In recent years, there has been an insatiable desire for faster computer processing data throughputs because cutting-edge computer applications involve real-time, multimedia functionality.

Graphics applications are among those that place the highest demands on a processing system because they require such vast numbers of data accesses, data computations, and data manipulations in relatively short periods of time to achieve desirable visual results.

These applications require extremely fast processing speeds, such as many thousands of megabits of data per second.

While some processing systems employ a single processor to achieve fast processing speeds, others are implemented utilizing multi-processor architectures.

In multi-processor systems, a plurality of sub-processors can operate in parallel (or at least in concert) to achieve desired processing results.

The dotted area 500, is the external processor, with the patent explaining that the memory it shares (514) with the internal processor could be DRAM, MRAM or SRAM, among others:

PE 500 is closely associated with a shared (main) memory 514 through a high bandwidth memory connection 516.

Although the memory 514 preferably is a dynamic random access memory (DRAM), the memory 514 could be implemented using other means, e.g., as a static random access memory (SRAM), a magnetic random access memory (MRAM), an optical memory, a holographic memory, etc.

accordance with an alternative embodiment, two processor elements may be cascaded by each employing its respective BIC in a coherent symmetric multiprocessor (SMP) interface (or BIF) configuration. The coherent SMP interface (BIF) of each processing element is coupled to one another to set up a coherent interface there between.